Designing with FPGAs & CPLDs
by:
Robert Zeidman
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Publisher:
CMP BOOKS,Sep-2002
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DESKTOP PUBLISHING Level:
ISBN: 1578201128
ISBN13: 9781578201129
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Choose the right programmable logic devices and development tools
Understand the design, verification, and testing issues
Plan schedules and allocate resources efficiently
Choose the right programmable logic devices with this guide to the technologies and internal architectures of Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). This complete reference is written in easy-to-understand language intended for engineers who are planning a CPLD-based or FPGA-based design; managers who need to plan, schedule, and budget a CPLD-based or FPGA-based design; and board-level designers who need to design CPLDs or FPGAs into a product. Experienced designers will find well-structured guidelines for future projects. The author explains the entire procedure for designing these devices from specification through production.
Programmable logic devices are explained in an overview, leading up to a detailed description of CPLDs and FPGAs. The various architectures are examined thoroughly along with the tradeoffs - allowing you to decide which particular device is right for your design. Engineers learn about important design, verification, synthesis, and testing issues for producing an optimized and reliable design as well as the different Electronic Design Automation (EDA) tools available. Engineering managers learn how to use the step-by-step Universal Design Methodology (UDM) to optimally allocate resources and to schedule and budget the development process accurately.
Bob Zeidman is the president of The Chalkboard Network, an e-learning company for high-tech professionals. He is also president of Zeidman Consulting, a hardware and software contract development firm. Since 1983, he has designed CPLDs, FPGAs, ASICs, and PC boards for RISC-based parallel processor systems, laser printers, network switches and routers, and other real-time systems. His clients have included Apple Computer, Cisco Systems, Ricoh Systems, and Texas Instruments. He is the author of Verilog Designer's Library, one of the most popular textbooks on verilog, Introduction to Verilog, as well as a number of engineering and business papers. Bob is also a senior member of the IEEE, has won several engineering and writing awards, and has taught engineering and business courses at conferences throughout the world. Bob holds a master's degree in electrical engineering from Stanford University and bachelor's degrees in EE and physics from Cornell University.
Table of Contents
Foreword
Preface
Acknowledgments
Chapter 1 Prehistory: Programmable Logic to ASICs
Programmable Read Only Memories (PROMs)
Programmable Logic Arrays (PLAs)
Programmable Array Logic (PALs)
The Masked Gate Array ASIC
CPLDs and FPGAs
Summary
Exercises
Chapter 2 Complex Programmable Logic Devices (CPLDs)
CPLD Architectures
Function Blocks
I/O Blocks2.4 Clock Drivers
Interconnect
CPLD Technology and Programmable Elements
Embedded Devices
Summary: CPLD Selection Criteria
Exercises
Chapter 3 Field Programmable Gate Arrays (FPGAs)
FPGA Architectures
Configurable Logic Blocks
Configurable I/O Blocks
Embedded Devices
Programmable Interconnect
Clock Circuitry
SRAM vs. Antifuse Programming
Emulating and Prototyping ASICs
Summary
Exercises
Chapter 4 Universal Design Methodology for Programmable Devices
What is UDM and UDM-PD?
Writing a Specification
Specification Review
Choosing Device and Tools
Design
Verification
Final Review
System Integration and Test
Ship Product!
Summary
Exercises
Chapter 5 Design Techniques, Rules, and Guidelines
Hardware Description Languages
Top-Down Design
Synchronous Design
Floating Nodes
Bus Contention
One-Hot State Encoding
Design For Test (DFT)
Testing Redundant Logic
Initializing State Machines
Observable Nodes
Scan Techniques
Summary
Exercises
Chapter 6 Verification
What is Verification?
Simulation
Static Timing Analysis
Assertion Languages
Formal Verification
Summary
Exercises
Chapter 7 Electronic Design Automation Tools
Simulation Software
Testbench Generators
In Situ Tools
Synthesis Software
Automatic Test Pattern Generation (ATPG)
Scan Insertion Software
Built-In Self-Test (BIST) Generators
Static Timing Analysis Software
Formal Verification Software
Place and Route Software
Programming Tools
Summary
Exercises
Chapter 8 Today and The Future
Cores
Special I/O Drivers
New Architectures
ASICs with Embedded FPGA Cells
Summary
Appendix A Answer Key
Appendix B Verilog Code for Schematics in Chapter 6
Glossary
References
About the Author
Index
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